The present invention relates generally to comparators, and more particularly to a comparator for comparing dual-coded data, such as can be used for fast address comparison in computer systems, for testing and diagnosis of software, or in digital control circuits for comparison of reference and actual values.
In some hardware comparators, the data is checked directly, bit by bit, using gates or comparators. However, with the bit width of data words used in current computer systems, this leads to a correspondingly large number of components. In many instances, these large numbers of components cannot be tolerated, because of the resulting space requirement.
U.S. Pat. No. 4,100,532 discloses a comparator provided with memory in which characteristic data are stored at specific addresses, which map the comparison data in question so that the data can be output by address control. By dividing the address lines into individual groups, the known device achieves a reduction in the required address space, and a 2-bit wide version of the memory makes it possible to provide information as to whether a currently accessed address is equal to or greater than the comparison address.
The present invention is directed to the problem of further developing hardware comparators for comparing dual-coded data by reducing the number of required components and by expanding their area of application.